1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having a multi-layer interconnection connecting an upper wiring and a metal wiring made of a copper type metal material, through a via hole.
2. Description of the Relates Art
A representative example of the conventional process for production of a semiconductor device having a multi-layer interconnection is described with reference to FIGS. 5 to 8. This example is a so-called dual damascene process wherein a lower wiring and an upper wiring are each formed so as to have a damascene interconnection.
On a semiconductor substrate (not shown) on which a device (e.g. transistor) has been formed, are formed a silicon oxide film 201 having a thickness of 100 nm and a HSQ (hydrogen silsesquioxane) film 202 having a thickness of 400 nm. Successively, thereon is formed a photoresist mask 203 having a predetermined pattern [FIG. 5(a)]. Dry etching is conducted using this mask to form, in the HSQ film 202, a groove for formation of buried lower wiring. Successively, ashing by oxygen plasma and cleaning by a cleaning solution containing an amine compound are conducted to peel the photoresist mask 203 [FIG. 5(b)]. conducted to peel the photoresist mask 203 [FIG. 5(b)].
Next, on the whole surface of the resulting substrate is formed, by sputtering, a TiN 204 film (thickness: 50 nm) as a barrier metal film. Thereon is formed a copper film 205 by sputtering, to fill the groove [FIG. 5(c)]. Successively, CMP (chemical mechanical polishing) is conducted to remove the unnecessary portions of the TiN film 204 and the copper film 205, formed outside the groove, to complete a lower wiring [FIG. 5(d)].
After the formation of the lower wiring, an HSQ film 206 having a thickness of 1,200 nm is formed by coating and subsequent firing. Thereon is formed a resist mask 207 having a pattern of via holes (diameter: 0.25 xcexcm) [FIG. 6(a)]. Dry etching is conducted using this resist mask 207 to form part of a via hole in the HSQ film 206. The dry etching is stopped before the bottom of the via hole formed reaches the copper film 205. As the etching gas, there is used, for example, a mixed gas containing C4F8 and Ar, or a mixed gas further containing O2. Successively, ashing by oxygen plasma and cleaning by a cleaning solution containing an amine compound are conducted to peel the resist mask 207 [FIG. 6(b)].
Next, a resist mask 208 is formed on the HSQ film 206 [FIG. 7(a)]. The width of opening of the resist mask 208 is made larger than the diameter of the resist mask 207 of FIG. 6(a). Dry etching is conducted using this resist mask 208, to form a hole having a T-shaped section in the HSQ film 206. As the etching gas, there is used, for example, a mixed gas containing C4F8 and Ar, or a mixed gas further containing O2. Successively, ashing by oxygen plasma and cleaning by a cleaning solution containing an amine compound are conducted to peel the resist mask 208 [FIG. 7(b)].
Next, on the whole surface of the resulting substrate is formed, by sputtering, a TiN film 209 (thickness: 50 nm) as a barrier metal film. Thereon is formed a copper film 211 by sputtering, to fill the hole having a T-shaped section [FIG. 8(a)]. Successively, the unnecessary portions of the TiN film 209 and the copper film 211, formed outside the hole are removed by CMP to complete an upper wiring (corresponding to the top of the T-shaped hole) and a via plug [FIG. 8(b)].
In the above-mentioned conventional production process, however, there have been cases that a leakage current flows in the inter-layer insulating film formed or the device (e.g. transistor) formed beneath the inter-layer insulating film causes malfunctioning.
The present inventor made an in-depth study on the causes of such phenomena and found out that contaminants consisting of copper and copper compounds remain on the inner walls of the via hole and groove for buried wiring both formed in the inter-layer insulating film and these contaminants cause the above phenomena.
In etching the inter-layer insulating film formed on a lower wiring, to form a via hole,the necessity of overetching invites partial etching of the copper constituting the lower wiringand generates metal contaminants. These metal contaminants ordinarily adhere to the inner walls of via hole, etc. in the form of a compound formed by a chemical reaction of copper with an etching gas component. The contaminants are impossible to remove by conventional cleaning using, for example, a cleaning solution containing an amine compound; therefore, formation of barrier metal film on inner walls of via hole, etc. is inevitably conducted in a state that the contaminants remain on the inner walls of via hole, etc. The contaminants remaining on the inner walls of via hole, etc., when placed in an electric field or heated, diffuse into the inter-layer insulating film, causing various problems such as current leakage and the like.
The phenomena are explained with reference to FIG. 9. In FIG. 9, on a silicon substrate 223 is formed a MOSFET comprising a source region 225, a drain region 226 and a gate electrode 224. The source region 225 is connected to a lower wiring consisting of a copper film 205, via a contact hole 221. This lower wiring is connected to a via hole 211 (including an upper wiring) consisting of a tungsten film. To the inner walls of the via hole and the buried wiring both formed in an HSQ film 206 adhere the metal contaminants 212 formed by the partial etching of the copper film 205 constituting the lower wiring. The metal contaminants 212, when undergoing heat history or placed in an electric field, migrate like the arrow marks shown in FIG. 9, reach a device (e.g. transistor) and allow the device to malfunction, or stay in the inter-layer insulating film and generate a leakage current.
These problems do not appear when aluminum is used as a material for wiring, but appear when a copper type metal is used as a material for wiring. It is because copper, as compared with aluminum, is significantly large in diffusion rate in insulating film.
To form a multi-layer. interconnection free from the above problems, it is necessary to conduct, after the formation.of a via hole and a buried wiring, cleaning which is different from conventional cleaning using, for example, a cleaning solution containing an amine compound. Since such cleaning aims at (1) cleaning the inside of via hole, (2) removing the metal contaminants which have adhered on the exposed surface of inter-layer insulating film, and (3) removing the metal contaminants which have adhered after dry etching, the cleaning has requirements different from those in the other steps of semiconductor device production. Description is made on this below.
Firstly, the above cleaning aims at cleaning the inside of via hole. Therefore, the shear force of the flow of cleaning solution does not easily reach the inside of via hole which is an area to be cleaned. Substantially no shear force is produced there particularly when the via hole formed has a small diameter. Thus, no physical cleaning action is expected and it is necessary to conduct sufficient cleaning by chemical cleaning action alone.
If mismatching of photoresist occurs at the time of via hole formation, there are cases that the portion of the HSQ film contacting with the lower wiring and facing the formed via hole, formed as a result of the mismatching is etched and a slit is formed at the portion (FIG. 16). In such a slit, no circulation of cleaning solution hardly takes place and cleaning under very sever conditions is necessary.
Secondly, the above cleaning aims at removing the copper type metal contaminants which have adhered on the exposed surface of inter-layer insulating film. Therefore, there naturally is a restriction as to the kind of the cleaning solution used. In recent years, a material of low dielectric constant has been widely used for the inter-layer insulating film of semiconductor device. As the material of low dielectric constant, there is preferably used a SOG (spin-on-glass) film, particularly a HSQ film. With such a film, the exposed surface thereof causes property change depending upon the kind of the cleaning solution used, resulting in increased dielectric constant. Therefore, it is necessary to select a cleaning solution which does not adversely affect. the dielectric constant of SOG film or the like. Further, the metal contaminants of copper type compounds which have adhered on the exposed surface of SOG film or the like, have high adhesivity to the surface, making very difficult the cleaning thereof.
Thirdly, the above cleaning aims at removing the copper type metal contaminants which have adhered after dry etching. Therefore, the cleaning of such metal contaminants must be conducted by an action different from that employed in removal of metal contaminants consisting of ordinary metals or oxides thereof. As mentioned above, the above cleaning aims at removing the metal contaminants generated, at the time of via hole formation, by the partial etching of the copper constituting the lower wring. These contaminants are in the form of a compound formed by a chemical reaction of copper with an etching gas component, have high adhesivity to inter-layer insulating film, particularly SOG film, and are difficult to remove by conventional cleaning for via hole inside.
As described above, to form a multi-layer interconnection free from current leakage, etc., it is necessary to conduct, after the formation of via hole and buried wiring, cleaning different from the conventional cleaning using, for example, a cleaning solution containing an amine compound.
For the removal of metal contaminants present inside via hole, cleaning by DHF (dilute hydrofluoric acid) is considered as one method. With this method, copper type metal contaminants can be removed to a certain extent, but no sufficient removal is obtained. Further, DHF causes etching of inter-layer insulating film, resulting in enlarged hole diameter. Enlargement of hole diameter is striking particularly when a SOG film is used.
The present invention has been completed in order to alleviate the above problems, and aims at sufficiently removing the copper type metal contaminants which have adhered to the inner walls of via hole and groove for buried wiring and thereby alleviating the current leakage in multi-layer interconnection and the malfunctioning of device.
According to the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of:
(A) a step of forming, on a semiconductor substrate, a metal wiring made of a metal material containing copper or a copper alloy,
(B) a step of forming an inter-layer insulating film on the metal wiring,
(C) a step of forming, at a predetermined position of the inter-layer insulating film, a via hole reaching the metal wiring by dry etching,
(D) a step of removing contaminants which consist of the metal material and/or the compound(s) thereof and which have adhered to the inner wall of the via hole as a result of the dry etching, by using a cleaning solution containing a complexing agent capable of forming a complex with the contaminants,.
(E) a step of forming a barrier metal film on the inner wall of the via hole and then forming an electrically conductive film on the whole surface of the resulting substrate so as to fill the via hole, and
(F) a step of removing the unnecessary portions of the electrically conductive film and the barrier metal film, formed outside the via hole, by etching or chemical mechanical polishing to obtain a flat surface.
In the present method of manufacturing a semiconductor device, the dry etching conducted in the step (C) invites adhesion of metal contaminants to the inner wall of the via hole formed by the dry etching. These contaminants are generated as a result of the etching of the metal material containing copper or a copper alloy, constituting the metal wiring, and are composed mainly of copper, a copper oxide(s) and a reaction product of copper and an etching gas.
The contaminants containing the oxide(s) and the reaction product of copper and an etching gas, adhering to the inner wall of the inter-layer insulating film are generally difficult to remove. In the present invention, the inner wall of via hole is cleaned using a cleaning solution containing a complexing agent capable of forming a complex with the above-mentioned contaminants, whereby the above-mentioned problems are solved.
According to the present invention, there is also provided a method of manufacturing a semiconductor device having a copper wiring, which comprises, after formation of a via hole, cleaning the inside of the via hole using a cleaning solution containing a complexing agent capable of forming a complex with contaminants of copper type metals.
In the, present invention, the xe2x80x9ccopper type metalsxe2x80x9d refer to metals consisting of copper and compounds thereof; and the xe2x80x9ccontaminants of copper type metalsxe2x80x9d refer to contaminants generated during the formation of via hole as a result of, for example, dry etching. In the present invention, these contaminants can be easily removed because they are cleaned using a cleaning solution containing a complexing agent capable of forming a complex with the contaminants.